Thin film transistors (TFTs) are used in the construction of active-matrix liquid-crystal displays, active-matrix organic light emitting diode displays, active-matrix e-ink electronic books and active-matrix image sensors. TFTs based on amorphous silicon suffer from low operating speed and lack of a p-type device, making it difficult to realize peripheral circuits. There is a drive to switch to polycrystalline silicon devices obtained from amorphous silicon.
Further, whilst large-area flat-panel liquid-crystal displays can use amorphous-silicon-based TFTs, for smaller area, higher information-content displays, it is recognized that polycrystalline-silicon-based, rather than amorphous-silicon-based, TFTs must be used. Polycrystalline-silicon-based devices can also be used in the fabrication of 3-dimensional integrated circuits. The traditional approach of increasing device density is to improve micro-lithography resolution, the cost of doing which is becoming increasingly prohibitive. An alternative to achieving higher device density is to stack polycrystalline-silicon-based devices of more relaxed lateral dimensions on top of single-crystal devices, potentially at a much reduced micro-lithography cost.
Polycrystalline silicon obtained by conventional low-pressure chemical vapor deposition suffers from relatively high process temperatures (620-650° C.) and poor material quality. Quality can be improved using high temperature annealing (above 1000° C.). However, this is only possible for much more expensive quartz substrates but not for inexpensive glass substrates.
One popular method currently used to form polycrystalline silicon from amorphous silicon is metal-induced crystallization (MIC). Conventional MIC calls for the introduction of a minimum amount of metal elements, necessary for the nucleation and growth of polycrystalline silicon from amorphous silicon, at a temperature between 400° C. to 600° C. Led by nodules of metal silicide at the crystallization front, elongated grains of polycrystalline silicon grow from each crystal nucleus. When the crystallization fronts from neighboring nuclei collide, a well defined collision interface, containing a relatively large amount of metal residual, is formed. Such metal residual is considered a contaminant and degrades the performance of the devices on the resulting polycrystalline silicon thin film.
Two of the more popular approaches to MIC are (1) blanket metal coverage leading to the crystallization of a large area within a short process time and (2) localized metal coverage leading to metal-induced lateral crystallization (MILC), requiring a long process time. For lower residual metal contamination and better device performance, MILC is presently preferred, though at the expense of a significantly longer process time.
Attempts have been made to reduce the amount of residual metal in polycrystalline silicon after it has been produced.
U.S. Pat. No. 6,821,828, issued on 23 Nov. 2004, to Mitsuhiro Ichijo, Taketomi Asami and Noriyoshi Suzuki, and entitled “Method of manufacturing a semiconductor device”, proposes performing metal-gettering after an MILC process, using a further amorphous silicon layer containing a noble gas.
U.S. Pat. No. 6,664,144, issued on 16 Dec. 2003, to Setsuo Nakajima and Hisashi Ohtani, and entitled “Method of forming a semiconductor device using a group XV element for gettering by means of infrared light”, proposes performing metal-gettering after an MILC process, using a further amorphous silicon layer doped with phosphorus.
U.S. Pat. No. 6,551,907, issued on 22 Apr. 2003, to Hisashi Ohtani, and entitled “Metal-gettering method used in the manufacture of crystalline-Si TFT”, proposes using a nickel-containing phosphosilicate glass layer, from which nickel is introduced to enhance crystallization at a low temperature. After crystallization, at a higher temperature, phosphorus is diffused out and getters the nickel.
U.S. Pat. No. 6,465,287, issued on 15 Oct. 2002, to Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa and Mitsuaki Osame, and entitled “Method for fabricating a semiconductor device using a metal catalyst and high temperature crystallization”, proposes performing a metal-gettering process, in an oxidation atmosphere containing halogen element, to MILC produced polycrystalline silicon, which consumes part of the polycrystalline silicon. This is undesirable for very thin films of polycrystalline silicon.
These four patents propose performing MILC and a gettering process one after the other, which will obviously lengthen the total process time.
US patent application publication 2002/0,192,884, published on 19 Dec. 2002, in the names of Chang, Ting-Chang and Chen, Ching-Wei, and entitled “Method for forming thin film transistor with reduced metal impurities”, proposes transforming amorphous silicon into polycrystalline silicon after it has already been patterned into source, drain and channel regions, with a gate insulating layer and a gate electrode atop the channel region and the source and drain regions heavily doped. The amorphous silicon film is deposited on a gettering layer. A nickel layer is deposited on top of the source and drain regions, the gate insulating layer and the gate electrode. The amorphous silicon is then crystallized, the source and drain regions by MIC and the channel region by MILC. During the crystallization process, nickel is gettered into the underneath gettering layer.
The presence of the bottom gettering layer and nickel gettered into it may affect the material quality and the characteristics of the devices built on the resulting polycrystalline silicon. Additionally, the gettering layer necessarily becomes part of the device.